fix(riscv): gate FP instructions and CSRs on mstatus.FS

[carlosqwqqwq]

Summary

RISC-V requires mstatus.FS=Off to make floating-point state inaccessible in every privilege mode. This change gates scalar/vector FP execution and fflags/frm/fcsr availability on FS != Off. The opt-in RISC-V JIT keeps FP state-sensitive instructions on the interpreter path because its native ABI does not carry privilege or mstatus.FS.

Validation

• fp_instructions_and_csrs_trap_when_fs_is_off: scalar/vector FP and FP CSR accesses with FS=Off trap in U/M mode; FS=Initial permits execution, and successful scalar/vector FP plus guest FP CSR writes transition FS to Dirty.
• jit_falls_back_for_fp_state_gates_at_o0_and_o2: JIT O0/O2 preserve the same traps for scalar FP, fcsr, and vector FP while recording an interpreter fallback.

Closes #317