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fix(riscv): validate vcompress destination alignment - #324

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carlosqwqqwq wants to merge 3 commits into
HexRaysSA:masterfrom
carlosqwqqwq:fix-riscv-vcompress-vd-align
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fix(riscv): validate vcompress destination alignment#324
carlosqwqqwq wants to merge 3 commits into
HexRaysSA:masterfrom
carlosqwqqwq:fix-riscv-vcompress-vd-align

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@carlosqwqqwq

@carlosqwqqwq carlosqwqqwq commented Aug 22, 2026

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Summary

Reject vcompress.vm encodings whose destination and source register groups are not aligned to their LMUL size. The illegal-condition path now checks both vd % emul != 0 and vs2 % emul != 0, alongside the existing vm, vstart, and source-overlap checks.

Validation

  • vcompress_rejects_misaligned_vd: e32,m2 cases with misaligned vd=v1 and misaligned vs2=v1 trap; the aligned control vd=v4, vs2=v8 executes.

Closes #319

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vcompress.vm accepts a misaligned destination register group

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