fix(riscv): support RV32 amocas.d register pairs

[carlosqwqqwq]

fix(riscv): support RV32 amocas.d register pairs

Summary

Accept RV32 AMOCAS.D with even rd/rs2 pairs and implement the 64-bit
compare, swap, and old-value writeback across the pair. RV64 behavior is
unchanged.

Validation

• Base: 7f162b19aeaa47825c82fb1c77ca042f535124e3.
• git apply --check --whitespace=error on the exact isolated base: passed.
• git diff --check: passed.
• Isolated exact RISC-V harness: cargo test --lib -- --nocapture — 181 passed,
  including rv32_amocas_d_decodes_and_uses_register_pairs.
• The regression also confirms that ordinary RV32 .D AMO encodings remain
  illegal; only Zacas AMOCAS.D uses the RV32 register-pair form.
• The post-fix full-source debug run reports 8263 passed, 3 failed, 2 ignored;
  the three failures are existing vector tests and reproduce on the same
  unpatched baseline, so none is introduced by this V-074 diff.
• Remote Linux, cross-build, native core tests, and rustfmt/clippy checks passed
  on head e1a8f7ff034c11cc01f0a4aa7bd7662b188d52cf. The shared
  build + boot job currently fails before reaching RAX code in
  microkernel/src/arch.rs because this runner's Rust/LLVM rejects existing
  sse/avx/avx2/avx512f target features; the exact-base Microkernel run passed.
  The RV32 oracle boundary remains documented in the Issue.

Closes #329

[carlosqwqqwq]

I rechecked the remaining red Microkernel check against the exact base and the PR file scope.

• This PR changes only src/isa/riscv/cpu.rs and src/isa/riscv/decode.rs; neither microkernel/src/arch.rs nor .github/workflows/microkernel.yml is part of the diff.
• On head e1a8f7f, the Microkernel run fails in Build microkernel for all three architectures, before the boot/RAX test step. The compiler reports enabling the 'sse' target feature on the current target is unsupported due to LLVM backend issues at the existing microkernel/src/arch.rs attributes on lines 311, 333, and 355.
• The same Microkernel workflow passed both build and boot on the exact base 7f162b19aeaa in the baseline run.
• On this PR head, the main CI run passed the native build matrix, core tests, Cross (including riscv64gc-unknown-linux-gnu), rustfmt, clippy, and the aggregate CI gate.

Based on this comparison, the remaining failure is caused by the shared workflow's moving nightly Rust/LLVM toolchain, not by this focused RISC-V patch. The workflow/toolchain issue should be handled separately so this PR remains scoped to RV32 AMOCAS.D.