Issues

• Build errors relating to const abuse

  riscv-collab/riscv-openocd#1323 · Filter by author nick-apitronix opened on May 8, 2026
  1

• OpenOCD increments dmi_busy_delay and idle_cycles too much during trigger examination

  riscv-collab/riscv-openocd#1322 · Filter by author taimur-silverliningeda opened on May 6, 2026

• Support for RISC-V RNMI registers

  riscv-collab/riscv-openocd#1320 · Filter by author kubeqz opened on Feb 13, 2026
  4

• Implement DMI behind Coresight DAP

  riscv-collab/riscv-openocd#1318 · Filter by author summershrimp opened on Jan 7, 2026
  3

• dcsr.stepie is default to zero although openocd set_maskisr is off

  riscv-collab/riscv-openocd#1317 · Filter by author fanghuaqi opened on Dec 31, 2025
  2

• Check the value read from target before performing address arithmetic based on it

  riscv-collab/riscv-openocd#1311 · Filter by author en-sc opened on Nov 5, 2025

• Drop RTI cycle in case DMI delay is zero

  riscv-collab/riscv-openocd#1310 · Filter by author en-sc opened on Nov 5, 2025
  2

• Assertion failure when force-reading a dirty register

  riscv-collab/riscv-openocd#1309 · Filter by author en-sc opened on Nov 5, 2025
  3

• No need for busy delays after a DMI NOP.

  riscv-collab/riscv-openocd#1308 · Filter by author en-sc opened on Nov 5, 2025
  2

• DMI busy is mishandled on Microchip PolarFire SoC

  riscv-collab/riscv-openocd#1307 · Filter by author en-sc opened on Nov 5, 2025
  5

• Memory burst writes with abstractauto can fail due to missing BUSY checks

  riscv-collab/riscv-openocd#1306 · Filter by author nadime15 opened on Nov 4, 2025
  8

• OpenOCD incorrectly attempts to write to read-only vector CSRs (vl, vtype, vlenb)

  riscv-collab/riscv-openocd#1305 · Filter by author nadime15 opened on Nov 4, 2025
  3

• Drop the use of has_sufficient_progbuf() with riscv_program_exec()

  riscv-collab/riscv-openocd#1301 · Filter by author en-sc opened on Oct 27, 2025
  4

• Update misa register when hart halted

  riscv-collab/riscv-openocd#1298 · Filter by author lz-bro opened on Oct 13, 2025
  4

• The logic around halt groups is broken by smp off; smp on sequence

  riscv-collab/riscv-openocd#1294 · Filter by author en-sc opened on Sep 22, 2025

• Prevent usage of the same coreid on the same debug module.

  riscv-collab/riscv-openocd#1293 · Filter by author MarekVCodasip opened on Sep 17, 2025
  2

• OpenOCD fails memory accesses (progbuf=disabled, sysbus=skipped, abstract=disabled) during peripheral polling and stepping

  riscv-collab/riscv-openocd#1291 · Filter by author Deeptha1212 opened on Sep 15, 2025
  9

• RISCV N-Trace

  riscv-collab/riscv-openocd#1289 · Filter by author oferShinaar opened on Sep 10, 2025
  1

• [Feature]: Zephyr-RTOS: multiple-threads debugging for RISC-V

  riscv-collab/riscv-openocd#1286 · Filter by author dangtaidat26 opened on Aug 25, 2025
  2

• Memory leak in riscv_openocd_step_impl()

  riscv-collab/riscv-openocd#1284 · Filter by author en-sc opened on Aug 18, 2025
  1

• Enable riscv virt2phys_mode to hw, insert breakpoing failed.

  riscv-collab/riscv-openocd#1278 · Filter by author weiqi7777 opened on Aug 7, 2025
  8

• Inquiry: Support for RISC-V Hypervisor (H-mode) Debugging in OpenOCD？

  riscv-collab/riscv-openocd#1277 · Filter by author Alan-19950616 opened on Aug 5, 2025
  3

• Unpredictable loading on slow simulators (progbuf)

  riscv-collab/riscv-openocd#1276 · Filter by author raamypi opened on Jul 13, 2025
  1

• Memory Sampling support for targets with last level write-back cache(s)

  riscv-collab/riscv-openocd#1275 · Filter by author raamypi opened on Jul 8, 2025
  3

• How can I control the time between writing to dmcontrol 0x80000003 and 0x10000001, when I give "reset halt" command to ocd

  riscv-collab/riscv-openocd#1272 · Filter by author kong-ling-hui opened on Jun 27, 2025
  2