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Pull requests: sonos/tract

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Pull requests list

onnx: fix GatherNd output shape inference
#2635 opened Aug 14, 2026 by czoli1976 Contributor Loading…
fix(linalg): fix tanh and gelu output range
#2633 opened Aug 13, 2026 by cverrier Contributor • Draft
Fix dropping of uninitialised memory in tensor0
#2632 opened Aug 13, 2026 by Ollie-Pearce Loading…
2
data: add an integer ULP bound to tensor comparison
#2631 opened Aug 13, 2026 by czoli1976 Contributor Loading…
data: let stack_tensors' block copy handle a non-trivial outer dimension
#2630 opened Aug 12, 2026 by czoli1976 Contributor Loading…
core,onnx: carry the recurrent product inside the fused GRU cell
#2628 opened Aug 12, 2026 by czoli1976 Contributor Loading…
core: size LstmEpilogue's row loop from the state, not the pre-activations
#2627 opened Aug 12, 2026 by czoli1976 Contributor Loading…
core,onnx: fuse the standard ONNX GRU cell into one GruEpilogue op
#2626 opened Aug 12, 2026 by czoli1976 Contributor Loading…
core/array: let Gather's block copy handle a non-trivial outer dimension
#2624 opened Aug 12, 2026 by czoli1976 Contributor Loading…
onnx/gru: keep the cell shape on the output update
#2623 opened Aug 12, 2026 by czoli1976 Contributor Loading…
core/array: rewrite constant-index ScatterNd block assignments to Slice/Concat
#2622 opened Aug 12, 2026 by czoli1976 Contributor Loading…
onnx/gru: one matmul per operand instead of one per gate
#2621 opened Aug 12, 2026 by czoli1976 Contributor Loading…
style: lint test and bench targets in CI
#2613 opened Aug 11, 2026 by cverrier Contributor Loading…
scan: pass tensors through OptScan when a single iteration covers the whole axis
#2606 opened Aug 10, 2026 by czoli1976 Contributor Loading…
riscv64: 4 of 4: RVV element-wise and reduction kernels
#2602 opened Aug 7, 2026 by czoli1976 Contributor Loading…
2
riscv64: 3 of 4: 8 and i32 RVV matmul kernels
#2601 opened Aug 7, 2026 by czoli1976 Contributor Loading…
1
riscv64: 2 of 4: 16 RVV matmul kernels behind Zvfh
#2600 opened Aug 7, 2026 by czoli1976 Contributor Loading…
1
riscv64: 1 of 4: RVV 1.0 f32 matmul kernels
#2599 opened Aug 7, 2026 by czoli1976 Contributor Loading…
7
linalg: AVX (no FMA) kernel tier for pre-Haswell x86
#2598 opened Aug 6, 2026 by czoli1976 Contributor Loading…
5
pulse: skip PulsePad's copy and symbol re-resolution on pass-through pulses
#2597 opened Aug 6, 2026 by czoli1976 Contributor Loading…
5
linalg,core: zero the padding lanes the mmm kernels compute on
#2596 opened Aug 6, 2026 by czoli1976 Contributor Loading…
5
linalg/wasm: make the relaxed-dot int8 path bit-exact on all engines
#2594 opened Aug 6, 2026 by czoli1976 Contributor Loading…
core/cnn: SIMD-vectorize BlockedConv's inner loop for WASM
#2592 opened Aug 6, 2026 by czoli1976 Contributor Loading…
linalg/wasm: fused simd128 f32 kernels for gelu, silu and erf
#2591 opened Aug 6, 2026 by czoli1976 Contributor Loading…
perf(linalg): run SiLU on a dedicated AVX-512 kernel
#2589 opened Aug 4, 2026 by cverrier Contributor • Draft
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