fix(riscv): preserve read-only machine interrupt pending bits

[carlosqwqqwq]

fix(riscv): preserve read-only machine interrupt pending bits

Summary

Apply the software-writable mip mask when servicing Csr::Mip writes, so
MTIP and MEIP remain controlled by the platform while writable supervisor and
software-pending fields retain their existing behavior. Add regression coverage
for direct writes, preservation of platform pending bits, and writable fields.

Validation

• Base: 7f162b19aeaa47825c82fb1c77ca042f535124e3.
• git apply --check on the exact isolated base: passed.
• git diff --check: passed.
• Isolated exact RISC-V harness: cargo test --lib -- --nocapture — 181 passed,
  including mip_writes_ignore_machine_timer_and_external_pending_bits.
• Full RAX 7f source archive with all four prepared patches: cargo test --lib —
  8601 passed, 0 failed, 2 ignored.
• Remote Linux, cross-build, and rustfmt/clippy checks passed. The shared
  build + boot job currently fails before reaching RAX code in
  microkernel/src/arch.rs because this runner's Rust/LLVM rejects existing
  sse/avx/avx2/avx512f target features; the exact-base Microkernel run passed.

Closes #328