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fix(riscv): preserve read-only machine interrupt pending bits - #334

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carlosqwqqwq:fix-riscv-mip-readonly-pending
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fix(riscv): preserve read-only machine interrupt pending bits#334
carlosqwqqwq wants to merge 1 commit into
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carlosqwqqwq:fix-riscv-mip-readonly-pending

fix(riscv): preserve read-only machine interrupt pending bits

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rustfmt + clippy
succeeded Aug 24, 2026 in 1m 41s